Federal Circuit Affirms PTAB: Viasat Error-Correction Patent Claims Found Obvious

The Federal Circuit has upheld a ruling by the Patent Trial and Appeal Board (PTAB, or the Board) that certain claims of Viasat Inc.’s data error-correction patent are unpatentable as obvious.

Viasat owns U.S. Patent No. 8,966,347 (the “’347 patent”), titled “Forward Error Correction with Parallel Error Detection for Flash Memories.”

Western Digital Technologies, Inc. filed a petition for inter partes review of claims 1–11 and 13–23 of the ’347 patent. The Board instituted review and, in its final written decision, found all challenged claims unpatentable as obvious in light of the prior art.

The key prior-art reference discussed on appeal is known as “Diggs.” As the court explained,

Diggs is directed to a system for adjustable error correction in solid-state storage systems, such as flash memory storage….. The Diggs system is very similar to the invention recited in the ’347 patent, in that the Diggs system, like the patented system, uses a controller and a decoding device to retrieve signals from the solid-state memory, to decode those signals, and to detect and correct the errors in the data revealed by the error correction mechanism.

As the court noted,

The [‘347] patent is directed to methods and systems for error correction in data retrieved from flash memory. Because flash memory is prone to an increasing error rate in the data over time, the invention is designed to modify the error correction process to make it more robust as the number of errors in the stored data begins to climb.

One method for correcting errors in flash memory data is to use a technique referred to as forward error correction (“FEC”), which generally uses an error correction code (“ECC”) to generate and store redundant information alongside the original data. When the original data is retrieved from memory, it is compared against the redundant information, which enables the system to detect and ultimately correct the corrupted data.

On appeal, the dispute focused on system claims 13–23 of the ’347 patent.

Independent claim 13 reads as follows:

13. A system comprising:

[a] an encoder to encode data using forward error correction coding;

[b] a flash memory to store the encoded data;

[c] a decoder to retrieve the encoded data stored in the flash memory to generate a data stream, and

[d] to process the data stream to correct errors in the data stream associated with the flash memory using at least a first error correction sub-module; and

[e] a controller…

According to the court, the key portions of claim 13 are limitations 13[c] and 13[d], which describe the decoder’s function as “to retrieve the encoded data stored in the flash memory to generate a data stream, and to process the data stream to correct errors in the data stream associated with the flash memory using at least a first error correction sub-module.”

The Board addressed Western Digital’s argument that the “decoder” in claim 13 is disclosed by the Diggs “Controller.” The Board noted that Figure 1 of Diggs depicts a Controller (component 114) that incorporates an ECC Detection and Correction module (component 125).

Before the PTAB, the parties focused on whether Diggs teaches a “decoder” that both “retrieve[s] the encoded data stored in the flash memory to generate a data stream,” as recited in limitation 13[c], and “process[es] the data stream to correct errors in the data stream,” as recited in limitation 13[d].

The parties agreed that Diggs’s Controller performs the function of retrieving the encoded data to generate a data stream, and that Diggs’s ECC Detection and Correction module performs the function of processing that data stream to correct errors.

They disagreed, however, about whether those functions had to be performed by a single component to satisfy claim 13’s “decoder” limitation.

The court noted that

Viasat argued that because the retrieval function in Diggs is performed by the Diggs Controller, and the correction function in Diggs is performed by the ECC Detection and Correction component, the two functions are not performed by a single decoder, but are performed by different components. Western Digital responded that in Diggs the ECC Detection and Correction module (125) is part of the Controller (114) and thus the same component performs the functions of data retrieval and correction.

The PTAB observed that the parties did not dispute that Diggs’s ECC Detection and Correction module is incorporated within the Diggs Controller. The Board therefore found that the Diggs Controller—together with the incorporated ECC Detection and Correction module—performed the two related functions attributed to the claimed “decoder,” as set forth in limitations 13[c] and 13[d].

The Board concluded that the difference between the relevant portions of Diggs and claim 13 was a “semantic discrepanc[y]” rather than a substantive distinction.

On that basis, the Board found claims 1–11 and 13–23 obvious in view of Diggs combined with another prior-art reference.

On appeal, Viasat argued that claim 13 requires a “decoder” that both “retrieve[s] the encoded data” and “correct[s] errors.”

The Federal Circuit found the argument unpersuasive. The court explained:

As shown in figure 1 of Diggs, the decoding mechanism in Diggs–the ECC Detection and Correction module (125)—is part of the Diggs Controller (114). For that reason, the Board found that the Controller in Diggs both receives the data stream and processes it, thus performing all the functions of the decoder recited in claim 13.

The court ultimately concluded:

While there is overlap in the Diggs circuitry that performs the functions of the controller and the decoder of the ’347 patent, nothing in the ’347 patent suggests that such overlap is impermissible. In fact, as noted above, the specification of the ’347 patent makes it clear that the components of the systems claimed in the patent—particularly the encoder, the decoder, and the controller—may be implemented by various circuits that individually or collectively are “adapted to perform some or all of the applicable functions in hardware.”

Taken together, the PTAB decision and the Federal Circuit’s affirmance provide a practical reminder that, in obviousness challenges, courts will often look past labels and focus on how the prior art’s architecture actually operates. Where a reference shows a controller and embedded sub-modules working together to perform the claimed functions, an argument that those functions must reside in a single, separately named “decoder” may not carry the day. For companies building or evaluating flash-memory and error-correction solutions, this case underscores the value of drafting and reviewing claims with implementation flexibility in mind—and of anticipating how closely related prior-art systems may be characterized in post-grant proceedings.