Federal Circuit Affirms Patent Board Decision for Intel

In a non-precedential decision, the Federal Circuit affirmed a decision of the Patent Trial and Appeal Board (PTAB or Board) that certain claims of Qualcomm’s U.S. Patent No. 8,838,949 (titled "Direct Scatter Loading of Executable Software Image from a Primary Processor to One or More Secondary Processor in a Multi-Processor System") were unpatentable for obviousness.

Back in 2017, Qualcomm had initiated actions against Apple, Inc. in district court and at the International Trade Commission (ITC), alleging that Apple infringed the '949 patent (and other patents) by making, selling, and using iPhone models that incorporated baseband processors made by Intel.

In 2019, Qualcomm and Apple settled all litigation worldwide between the two companies, and Qualcomm agreed to license the patents to Apple for six years (and two additional years if Apple wished).

As explained in the court’s 2021 previous decision on the dispute, Qualcomm’s patent

addresses multi-processor systems in which software stored in non-volatile memory coupled to a first processor is to be used by a second processor. The patent describes and claims systems, methods, and apparatuses for efficiently retrieving an executable software image from the first processor's non-volatile memory and loading it for use by the second processor.

Intel Corp. challenged all claims of the '949 patent as unpatentable for obviousness in three inter partes reviews (IPRs) before the Patent and Trademark Office.

The PTAB issued a final written decision holding that Intel had proved unpatentable claims 10, 11, 13–15, and 18–23 of the patent, but not claims 1–9, 12, 16, and 17.

On remand from the 2021 decision, the Board majority changed its earlier construction, which excluded “a temporary buffer” from the scope of “hardware buffer” (and on that basis rejected Intel’s unpatentability challenges), to a broader construction, under which a “hardware buffer” is “not limited to a ‘permanent’ buffer.”

Claims 1 and 2 are representative for the claim-construction issue on appeal. They recite:

1. A multi-processor system comprising:

a secondary processor comprising:

system memory and a hardware buffer for receiving an image header and at least one data segment of an executable software image, the image header and each data segment being received separately, and

a scatter loader controller configured:

to load the image header, and

to scatter load each received data segment based at least in part on the loaded image header, directly from the hardware buffer to the system memory;

a primary processor coupled with a memory, the memory storing the executable software image for the secondary processor; and

an interface communicatively couples the primary processor and the secondary processor, the executable software image being received by the secondary processor via the interface.

2. The multi-processor system of claim 1 in which the scatter loader controller is configured to load the executable software image directly from the hardware buffer to the system memory of the secondary processor without copying data between system memory locations on the secondary processor.

The parties disagreed about what’s required for a buffer to be a “hardware buffer.”

Intel contended that a buffer is a “hardware buffer” if the memory cells used by the buffer are ‘physically separate’ from the memory cells into which the software is loaded and from which the processor executes it (‘system memory’).”

Qualcomm proposed a narrower definition, in which “a buffer is a hardware buffer only if its memory cells are never used for system memory, rather than assigned to be used for that function (allocated) upon the turning on of power (or runtime).”

The Federal Circuit noted that neither party provided “an illuminating or persuasive explanation of its position.”

Thus, the court turned to the specification and prosecution history.

The court found that

within the specification, the term “hardware buffer” appears three times. … (“The system includes a secondary processor having a system memory and a hardware buffer for receiving at least a portion of an executable software image. The secondary processor includes a scatter loader controller for loading the executable software image directly from the hardware buffer to the system memory.”); …(“In one aspect, the executable software image is loaded into the system memory of the secondary processor without an entire executable software image being stored in the hardware buffer of the secondary processor.”)

However, said the court, those uses of the phrase do not indicate in any way why either the Intel view or the Qualcomm view of the phrase is the right one.

The court noted that “Prosecution history can illuminate a term’s meaning even when the patentee has not explicitly made relevant disclaimers.”

Also, prosecution history can be telling about how a patentee expects a relevant artisan to understand a term, even if what a relevant artisan is expected to infer about a term’s scope points in the direction of broadening rather than narrowing.

In this case, the Patent and Trademark Office first rejected the patent as anticipated by the Svensson prior art. The patent examiner mapped the claim phrase “hardware buffer” onto the intermediate storage area of Svensson—the same component of the same prior art Intel relied on as teaching the hardware buffer limitation in its obviousness challenge to the patent.

According to the court,

when Qualcomm responded to the examiner’s initial rejection, it did not expressly or implicitly challenge the examiner’s characterization of the intermediate storage area as a hardware buffer; it instead modified the claims to make clear that the process its buffer performed was different from that of Svensson’s intermediate storage area.

Although silence on a point that arises during patent prosecution may not often be properly given significance, said the court, in this case, the court found the silence “telling.”

The court noted that in response to a patent examiner rejection, Qualcomm did not even hint, let alone declare, that the Svensson [prior art] intermediate storage area—undisputedly allocated at runtime—was outside its claimed ‘hardware buffer.’

Thus, although the court felt that “there is something to be said for each side’s view of how to read the claim phrase ‘hardware buffer,’” there was no need to decide which meaning was better.

The court concluded:

This case is governed by the broadest-reasonable-interpretation standard, … which recognizes the distinctive duty of applicants or patentees to respond to uncertainty of scope by making clarifying changes, …. We conclude that Qualcomm has not persuasively shown the Board majority’s current claim construction to be unreasonable. We therefore affirm the Board’s claim construction and its resulting unpatentability determinations.